1. Field of the Invention
This application relates to phase detectors and more particularly to linear phase detectors and associated charge pump circuits.
2. Description of the Related Art
FIG. 1A illustrates a simplified high level block diagram of a phase-locked loop 150. A reference clock (REFCLK) supplied on node 151 is received by the phase/frequency detector 153, which also receives a feedback clock (DIVCLK) from the divider circuit 155 on node 156. The phase detector detects the difference between the reference clock and the feedback clock and the charge pump 157 generates a charge corresponding to that difference to drive the voltage controlled oscillator (VCO) 159. In that way the VCO output is adjusted up and down to remain “locked” to the reference clock.
An exemplary prior art phase detector is shown in FIG. 1B and its operation is described in FIG. 1C. When the REFCLK supplied to flip flop 101 leads the DIVCLK supplied to flip-flop 102 a pulse on UP is created as shown in FIG. 1C. In addition, when DIVCLK transitions then from a 0 to a 1 a RESET signal is asserted by AND gate 103, and a short pulse on DOWN is created whose length is determined by the delay through the reset path. The UP and DOWN pulses are used to control the exemplary charge pump shown in FIG. 1D.
However, the charge pump illustrated in FIG. 1D utilizes separate current sources 121 (IP) and 123 (IN) to control the charge supplied to control the oscillator. Those current sources are not absolutely identical, which results in a nonlinearity in a phase error transition region around 0 as shown in FIG. 1E. That approach may be acceptable for phase-locked loops in which the PLL output is an integer multiple of the reference clock. However, such nonlinearity is unacceptable for fractional-N phase-locked loops.
Accordingly, it would be desirable to provide a linear phase detector that avoids the non-linearity problem associated with the charge pump shown in FIG. 1D.